Memory bandwidth is the rate at which information might be read from or stored into a semiconductor memory by a processor. Memory bandwidth is often expressed in items of bytes/second, though this may vary for techniques with pure information sizes that aren't a a number of of the commonly used 8-bit bytes. Memory bandwidth that is marketed for a given memory or system is normally the maximum theoretical bandwidth. In observe the noticed memory bandwidth will probably be lower than (and is assured to not exceed) the advertised bandwidth. A wide range of laptop benchmarks exist to measure sustained Memory Wave Routine bandwidth using a wide range of entry patterns. These are meant to provide insight into the memory bandwidth that a system should maintain on numerous classes of actual purposes. 1. The bcopy convention: counts the quantity of data copied from one location in memory to another location per unit time. For example, copying 1 million bytes from one location in Memory Wave to a different location in memory in one second would be counted as 1 million bytes per second.

The bcopy convention is self-consistent, but will not be easily extended to cowl circumstances with more advanced access patterns, for instance three reads and one write. 2. The Stream convention: sums the quantity of data that the applying code explicitly reads plus the quantity of knowledge that the applying code explicitly writes. Utilizing the previous 1 million byte copy example, the STREAM bandwidth could be counted as 1 million bytes learn plus 1 million bytes written in one second, for a complete of 2 million bytes per second. The STREAM convention is most instantly tied to the consumer code, but may not rely all the data site visitors that the hardware is definitely required to carry out. 3. The hardware convention: counts the precise quantity of knowledge read or written by the hardware, whether the data movement was explicitly requested by the user code or not. Utilizing the identical 1 million byte copy instance, the hardware bandwidth on pc programs with a write allocate cache policy would include an extra 1 million bytes of visitors as a result of the hardware reads the target array from memory into cache earlier than performing the stores.

This provides a complete of three million bytes per second actually transferred by the hardware. The hardware convention is most instantly tied to the hardware, but could not symbolize the minimum amount of knowledge visitors required to implement the user's code. Quantity of knowledge transfers per clock: Two, within the case of "double knowledge charge" (DDR, DDR2, DDR3, DDR4) memory. Memory bus (interface) width: Every DDR, DDR2, or DDR3 memory interface is 64 bits huge. Number of interfaces: Fashionable personal computer systems sometimes use two memory interfaces (dual-channel mode) for an efficient 128-bit bus width. This theoretical most memory bandwidth is referred to because the "burst charge," which may not be sustainable. The naming convention for DDR, DDR2 and DDR3 modules specifies either a most pace (e.g., DDR2-800) or a most bandwidth (e.g., PC2-6400). The speed score (800) isn't the maximum clock velocity, but twice that (because of the doubled knowledge fee).

The specified bandwidth (6400) is the maximum megabytes transferred per second using a 64-bit width. In a twin-channel mode configuration, that is successfully a 128-bit width. Thus, the memory configuration in the example will be simplified as: two DDR2-800 modules working in twin-channel mode. Two memory interfaces per module is a standard configuration for Pc system memory, but single-channel configurations are frequent in older, low-end, or low-power units. Some private computers and most trendy graphics playing cards use more than two memory interfaces (e.g., four for Intel's LGA 2011 platform and the NVIDIA GeForce GTX 980). High-performance graphics playing cards working many interfaces in parallel can attain very high whole memory bus width (e.g., 384 bits in the NVIDIA GeForce GTX TITAN and 512 bits within the AMD Radeon R9 290X utilizing six and eight 64-bit interfaces respectively). In methods with error-correcting memory (ECC), Memory Wave the additional width of the interfaces (typically seventy two rather than 64 bits) is just not counted in bandwidth specs as a result of the extra bits are unavailable to store person data. ECC bits are higher considered a part of the memory hardware quite than as info saved in that hardware.